CMOS imagers are interesting candidates to replace traditional imaging sensors used in e.g. medical applications, because of their ability to integrate on-chip the read-out circuitry, data processing facilities and interfacing. Such integration, particularly by removing the need for external bond-wired chip-to-chip connections, offers significant performance advantages as well as cost-savings.
Basic building blocks of a typical high sensitivity photosensitive system are formed by a combination of a photodiode and a buffer stage, of which the latter transforms the high-impedance photodiode output to a lower impedance in order to allow subsequent processing of the detected signal. A key performance parameter for such a system is the total input capacitance of the photodiode and buffer, which directly determines the sensitivity in terms of the change in voltage per detected photon.
FIG. 1a shows a typical (so-called 3T) prior art pixel architecture, including relevant parasitic capacitances 131-133. The pixel architecture comprises a photodiode 102 coupled to a reset transistor 104, which is coupled to output node 120 via a source following transistor 106. The reset transistor 104 has in input terminal 110 for receiving a reset pulse. Operation of such a pixel is straightforward and involves two different phases (FIG. 1b). During a first (reset-) phase, the photodiode node is set to VD by applying a positive pulse on the reset transistor 102. After switching off this transistor, the photodiode node is essentially left floating as it is not electrically connected to any terminal. Incoming photons, indicated by the wavy arrow with label hv, result in a discharging of the diode resulting in, depending on the intensity of the incoming light, a gradual decrease in bias on an output node, as indicated by transient 140. The sensitivity of such a system is determined by the total capacitance Ctot seen by the photodiode node,
            C      tot        =                  C        pd            +              C        gd        SF            +              C        gs        reset                        Δ      ⁢                          ⁢      V        =                  qn        ph                    C        tot            
where ΔV is the voltage drop induced by nph collected photons.
It is noted that the sensitivity is independent on the gate-source capacitance CgsSF of the source follower (SF) 106, as the SF's source voltage exactly follows that of the photodiode 102 (ΔV=Vpd−Vout≈Vt=constant). This observation that two nodes with identically varying bias are not capacitively coupled has been extensively used when designing low-input capacitance buffers. Using discrete components, one can simply bootstrap the supply bias and ground node to the output by means of operational amplifiers, resulting in an effective input capacitance reduction of the buffer.
A much simpler, yet as effective, implementation for integrated circuits is shown in FIG. 2, which depicts a simple input buffer capacitance reduction. Two bandpass circuits are shown. The left circuit illustrates a FET in a source follower configuration. R is a resistor for testing the performance of the source follower (SF). When R=0, the source follower has a nearly unity gain for a range of frequencies from 10 Hz to 10 kHz. With R=1000 MΩ the gain decreases with increasing frequency. The right circuit illustrates a cascaded source follower configuration (CSF). Under similar operating conditions, the bandpass with R=1000 MΩ is increased by an order of magnitude. This is described in more detail in R. P. Scobey et al., “A simple circuit to reduce the input capacitance of microelectrode amplifiers”, IEEE trans. Biomed. Eng. 28, pp. 358-359, 1981.
The above solutions effectively compensate for stray capacitances of an input buffer, with a possibility to also include compensation for the stray capacitance of an input wire. In such solutions, the only significant capacitances left are those of components attached to the input node of the buffer, e.g. the photodiode and reset transistor. The latter can be compensated for by means of active compensation. Thereto, as shown in FIG. 3, an extra capacitor C2 is added to the input node, which is then driven at a given amount of feedback bias. This feedback loop is not explicitly shown in FIG. 3, but is disclosed in more detail in S. Brigati et al., “Active compensation of parasitic capacitances for very high frequency CMOS DACs”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1208-1211, 1993
Some medical applications typically require an extremely high sensitivity, to be able to measure for example very low levels of fluorescence induced by biomarkers. As a consequence, such systems require relatively large pixels to collect as many photons as possible with, as discussed above, the lowest possible pixel capacitance. It will be apparent to the skilled person that these requirements counteract each other, even when using diffusion-based designs with reduced cathode area. This is a major drawback of these prior art arrangements.
Apart from just high sensitivity and large area, the above and prior art detectors also need extremely low leakage currents, in order to be able to actually detect a low number of emitted photons. Again, requirements for low leakage as well as low capacitance counteract each other here. As surface leakage effects are typical a dominant mechanism at room temperature, as compensation, low leakage cathodes require some amount of field shaping around its perimeter. Gated diodes have been used as an effective means to suppress such leakage currents, with added benefit of improving radiation hardness. An example of such a solution can for instance be found in EP 1798575 A1.
Low leakage may be achieved by bringing the surface into slight accumulation, which for an n+ cathode photo-detector corresponds to biasing the outer gate of the diode around or slightly below 0V. As the depletion region width between the n+ cathode and the p+ anode can easily be of the order of several microns compared to the gate oxide thickness of several nanometers only, it follows directly from the capacitance equation C=A∈0∈r/t, t being the oxide thickness, that such gates quite easily dominate the total capacitance.
Hence, state of the art photodiodes typically feature a capacitance that is relative large, which limits the sensitivity of imaging systems in which they are integrated. As explained above, such capacitance can be reduced by active compensation, although process variations will typically limit such an approach to an improvement of around one order of magnitude only. In addition, active compensation adds to the complexity, i.e. cost, of the overall photodiode implementation. Hence, it would be advantageous to reduce the actual photo-diode capacitance, thereby limiting or altogether avoiding the amount of capacitance that needs to be compensated for.
The present invention is aimed at providing an improved photosensitive system overcoming one or more of the above disadvantages, and at the same time not jeopardizing other characteristics of an improved photosensitive system.